דרושים בתחום תפקידים נוספים

A leading provider of Asic and Cot desighn is looking for a Rtl designer
As a member of SoC/ASIC Logic Design team, you will have responsibilities of top level and/or complex blocks of a SOC, across all phases of Front-End design, including micro-architecture specification, RTL code development, debug of complex logic in high performance, and low power design.

minimum 3 years hands-on RTL coding in Verilog.
Experience with VCS, Verdi, and Spyglass (or similar tools).
Experience with block definition or micro architecture spec development.
Experience working with SVN and bug tracking.
Knowledge of System Verilog and C.