תיאור תפקיד:
A FPGA Engineer - developing our next-generation System
As a key member of FPGA team, play a crucial role in designing and implementing complex FPGA modules that form the core of our state-of-the-art communication system.
Define, architect, and develop complex FPGA modules for Company's next-generation wireless modem.
Plan micro-architecture and perform RTL coding.
Conduct simulation, debugging, and FPGA backend tasks (synthesis, timing closure).
Verify, validate, and integrate designs.
Collaborate with cross-functional teams to bring innovative ideas to life.
דרישות:
BS/MS in Electrical Engineering from leading universities with emphasis on signal-processing/communication.
3+ years of experience in digital design, communications, networking, and DSP block development.
Excellent teamwork and independent working abilities.
Strong communication skills.
Strong background in FPGA development and Xilinx tools.
Advantages
Knowledge of SystemVerilog.
Background in board design (digital, analog).
Familiarity with Linux.
Understanding of UVM (Universal Verification Methodology).
Experience in lab work (debugging, communication measurement equipment).
היקף משרה:
משרה מלאה
קוד משרה:
832575
אזור:
מרכז - תל אביב, פתח תקווה, רמת גן וגבעתיים, בקעת אונו וגבעת שמואל, מודיעין
שרון - חדרה וזכרון יעקב, נתניה ועמק חפר, רעננה, כפר סבא והוד השרון, ראש העין, הרצליה ורמת השרון
צפון - גליל, טבריה והכנרת, עפולה, נצרת ובית שאן, עכו, נהריה והגליל המערבי, קריות ועמק זבולון, חיפה והכרמל, גולן
השפלה - ראשון לציון ונס- ציונה, רמלה לוד, רחובות
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תיאור תפקיד:
We are seeking a highly skilled Senior Analog/Mixed-Signal Designer to join our experienced team. The ideal candidate will contribute to the realization of custom, end-to-end, state-of-the-art ASICs, with responsibilities spanning the development of Analog, Digital, and Mixed-signal circuits for advanced communication systems.
דרישות:
Analog Design Expertise:
Proven hands-on experience on key analog building blocks such as: LDO, BGR, OPAMP, etc...
Deep understanding of Analog design trade-offs, stability, noise, and power-performance optimization.
Excellent knowledge of Cadence Virtuoso and related tools suites for analog designs (IO planning, EMIR, LVS, QRC, …)
Digital Design Expertise:
Strong foundation in digital logic design and ASIC implementation flow.
Experience with Cadence tools for digital synthesis and backend flow (synthesis, place & route, timing closure).
Proficient in writing synthesizable, modular Verilog RTL for a variety of digital logic blocks, including control logic, data-paths, finite state machines, and timing-critical pipelines.
Mixed-Signal Design expertise:
Track record in one or more of the following areas:
Proven experience on state-of-the-art ADC architectures such as: Pipeline ADCs, Delta-Sigma ADCs for high-resolution applications.
Understanding of high-speed PHY and PCS SerDes blocks with proven experience on Tx (high-speed driver, FFE, serializers) and/or Rx (CTLE, VGA, DFE, CDR, deserializers ) blocks.
היקף משרה:
משרה מלאה
קוד משרה:
15738
אזור:
מרכז - תל אביב, פתח תקווה, רמת גן וגבעתיים, בקעת אונו וגבעת שמואל, חולון ובת-ים, מודיעין, שוהם
שרון - חדרה וזכרון יעקב, נתניה ועמק חפר, רעננה, כפר סבא והוד השרון, ראש העין, הרצליה ורמת השרון
השפלה - ראשון לציון ונס- ציונה, רמלה לוד, רחובות, יבנה
אילת - אילת והערבה
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תיאור תפקיד:
We are seeking a skilled FPGA Designer and Verification Engineer to join our dynamic team. The ideal candidate will be responsible for designing, implementing, verifying FPGA-based solutions for various applications and Integrating 3rd party IPs
The position is located at the company site in Sderot
Key Responsibilities:
Design and develop FPGA-based solutions using VHDL/Verilog
Create and maintain detailed design specifications and documentation
Develop and implement verification plans for FPGA designs
Design and maintain testbenches for FPGA projects
Conduct functional simulations and analyze results to ensure design integrity
Collaborate with design engineers to understand design intent and constraints
Debug and resolve issues found during verification
Stay up-to-date with industry best practices in FPGA design and verification
דרישות:
Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field
Proven experience of VHDL logic design principles along with timing, area and power implications
Experience with creation of complex designs including coding and integration of 3rd party IPs
היקף משרה:
משרה מלאה
קוד משרה:
4242
אזור:
דרום - אשדוד, קרית גת, באר שבע, דימונה, אשקלון, קרית מלאכי, ערד וים המלח
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