דרושים בתחום וריפיקציה / ולידציה

1. Title:
SW Validation Engineer
2. Key Responsibilities
" New Feature Verification and Testing, Defect Regression, Automation test framework and code.
" Implementation Developing automated test cases for new products & Sustaining existing products.
" Will be deeply involved in the process of developing a new features.
3. Education
" B.Sc. in Electronics Engineering, Computer Science or SW Engineering - Must
4. Experience
" At least 1-year experience with manual & automation testing - Must
" In -depth knowledge of writing and executing test plans (STP/STD/STR) -Must
" Hands-on experience in verification tools and methodologies
" Experience in QA Automation methodologies, tools and best practices
" Experience in C# \ JAVA programming - Advantage
" Using VSTS\TFS tool - major advantage
5. Required skills
" Team player and a self-learner.
" Independent- Ability to work under minimal supervision
" Sticks to the task from the beginning to end

Responsibilities:
Investigate, invent, develop, innovate and improve challenging verification environments, from block-level to chip-level.
Working with sophisticated verification methodologies implementing System On Chip flows.
Close collaboration with the Design team, and supporting SW and Production teams.
Acquiring thorough knowledge and understanding of cutting edge industry technology and standards in various fields (communications, processors, interconnect, …).

Requirements:
B.Sc. in Electrical or Computer Engineering/Computer science from an established university
At least 3 years of experience in the Verification flow of complex designs from test plan definition to coverage closure
Experience in Specman – an advantage
Experience in UVM – an advantage
Background in System-On-Chip flows and on-chip interconnect protocols – an advantage

Personal skills:
Team player with proactive attitude
Thinker, self-learning, curious and motivated
Capable of understanding high level system flows and constraints

BSC in Electrical Engineering – from a well-known university
At least 2 years' experience as verification engineer
Knowledge in specman - an advantage
Knowledge in uvm – an advantage

BSc / MSc. in Electronics Engineering from a known university 
More than 3 years of experience in VLSI logic design in a known semiconductor company
Understanding and experience in a VLSI design flow: micro-architecture, logic design, verification, physical design, production tests and post-silicon