דרושים בתחום וריפיקציה / ולידציה

Proven FPGA/ASIC verification experience – 7 years
Experience in FPGA UVM/OSVVM methodologies and Assertion Based methodologies
Complex FPGA verification using Verilog/VHDL/SystemC
Experience in C/C++ verification environment
Experience in Linux OS as verification environment
Experience in Shell scripts in Linux (Bash, TCSH), TCL scripts
Experience in FPGA simulator tools (Modelsim and similar), Formal Verification tools and STA tools
Experience in FPGA Evaluation Boards, EVE, Palladium, Pearl, Matlab or Python would be an advantage
Responsibility on the FPGA verification infrastructure of the company
Documentation support

BSc/MSc Degree in Electrical Engineering/Computer Science
Innovative approach
Ability to learn new technologies quickly without guidance
Ability to work independently and as part of a team
Ability to learn and adjust regulation and standards
Strong interpersonal, written and verbal communication skills
Willingness to work hard to meet tough deadlines
Professional English

Responsible for all design activities including: uArch, coding, debug, timing, power, area, performance and support

Responsible for verification activities including verification strategy and plan, environment, coverage, test plan, debug and reach verification goals

Fully aware of IP factory (parametric design, smooth integration, etc)

Working tightly with architecture team

Good system and verification knowledge

Technical knowledge

Micro arch definition

Verilog coding

SV/UVM/Specman – an advantage

Lint tools

Timing, power and area

Synchronization for multiple clocks domains