דרושים בתחום וריפיקציה / ולידציה

• Min 4 years experience in Verification
• Have advanced knowledge of Digital VLSI architecture/design
• Need to have in-depth knowledge of verification flow and have experience with the full verification life cycle
• Familiarity with verification environments, SystemVerilog an advantage
• Knowledge in networking and wireless chips verification - an advantage
• Familiar with unix/linux and scripting languages (perl / TCL/ csh) - an advantage
• Good communication & teamwork skills

ncludes hands-on ASIC verification environment development for full chip, sub-cluster and unit levels within a wining VLSI team and startup company.
Responsibility for generation and execution of verification plan for challenging digital blocks/chip.
Development of System Verilog, UVM based protocol/traffic generators, monitors, checkers and coverage.

Job requirement:
- B.Sc. in Electrical Engineering from known university
- Minimum 2 years of experience in ASIC verification from semiconductor companies
- Knowledge and experience in System Verilog and UVM
- knowledge of verification flow (block level & full chip verification)
- Knowledge in scripting languages such as Python or Perl - Advantage
- Very good communication skills

BSC in Electrical Engineering – from a well-known university
At least 2 years' experience as verification engineer
Knowledge in specman - an advantage
Knowledge in uvm – an advantage

BSc / MSc. in Electronics Engineering from a known university 
More than 3 years of experience in VLSI logic design in a known semiconductor company
Understanding and experience in a VLSI design flow: micro-architecture, logic design, verification, physical design, production tests and post-silicon