דרושים בתחום וריפיקציה / ולידציה

BSC in Electrical Engineering – from a well-known university
At least 2 years' experience as verification engineer
Knowledge in specman - an advantage
Knowledge in uvm – an advantage

BSc / MSc. in Electronics Engineering from a known university 
More than 3 years of experience in VLSI logic design in a known semiconductor company
Understanding and experience in a VLSI design flow: micro-architecture, logic design, verification, physical design, production tests and post-silicon

1. Title:
SW Validation Engineer
2. Key Responsibilities
" New Feature Verification and Testing, Defect Regression, Automation test framework and code.
" Implementation Developing automated test cases for new products & Sustaining existing products.
" Will be deeply involved in the process of developing a new features.
3. Education
" B.Sc. in Electronics Engineering, Computer Science or SW Engineering - Must
4. Experience
" At least 1-year experience with manual & automation testing - Must
" In -depth knowledge of writing and executing test plans (STP/STD/STR) -Must
" Hands-on experience in verification tools and methodologies
" Experience in QA Automation methodologies, tools and best practices
" Experience in C# \ JAVA programming - Advantage
" Using VSTS\TFS tool - major advantage
5. Required skills
" Team player and a self-learner.
" Independent- Ability to work under minimal supervision
" Sticks to the task from the beginning to end

Verification Engineer

• Min 4 years experience in Verification
• Have advanced knowledge of Digital VLSI architecture/design
• Need to have in-depth knowledge of verification flow and have experience with the full verification life cycle
• Familiarity with verification environments, SystemVerilog an advantage
• Knowledge in networking and wireless chips verification - an advantage
• Familiar with unix/linux and scripting languages (perl / TCL/ csh) - an advantage
• Good communication & teamwork skills

Verification Engineer

Desired Skills and Experience:
• Min 4 years experience in Verification
• Have advanced knowledge of Digital VLSI architecture/design
• Need to have in-depth knowledge of verification flow and have experience with the full verification life cycle
• Familiarity with verification environments, SystemVerilog an advantage
• Knowledge in networking and wireless chips verification - an advantage
• Familiar with unix/linux and scripting languages (perl / TCL/ csh) - an advantage
• Good communication & teamwork skills