דרושים בגולן- משרות פנויות באלקטרוניקה וחשמל

לחברה בהוד השרון SOC ASIC Design Engineer

Requirements:
• BSc with excellence in Electrical/Computer Engineering
• At least 3 years of experience in ASIC design
• Experience in SoC design - advantage
• Background in processors architecture, wireless communication protocols, very low power design - advantage
• Experience in system performance and power analysis - advantage
• Knowledge in Verilog, Specman and scripting languages - advantage

· First or Second degree in EE, CE or equivalent
· At least 7 years of experience in RTL logic design
· Experience with Xilinx - Advantage
· Experience & Knowledge with System Verilog - Strong Advantage
· Knowledge in synthesis and timing analysis - Advantage
· Experience in multi clock and high frequencies designs - Advantage
· Experience in standard protocols such PCIe, UFS and DDR3 – advantage
· Deep knowledge of the following tools:
o ISE/Vivado – advantage
o NCSim – advantage
o Synplify
· Knowledge with Perl/python – advantage
· Knowledge simulation environment System Verilog based – advantage
· Experience in board design would be an added advantage
· Good communication and/or interaction skills among groups inside and outside of Israel
· Ability to communicate multiple interfaces inside the company
· Innovation capabilities
· Team worker

MSc in Electrical Engineering or higher
3+ years of developing algorithms in communications, signal processing, statistical analysis and probability methods
Programming skills in MATLAB and C/C++
Experience with Radar systems - an advantage
Experience with developing embedded SW - an advantage
Automotive industry experience - an advantage

BSC in Electrical Engineering – from a well-known university
At least 2 years' experience as verification engineer
Knowledge in specman - an advantage
Knowledge in uvm – an advantage

7+ years of VLSI front end design experience.
Has experience with leading a design team.
Must knowledge in wireless communication technologies.
Ability to architect (high level & micro level) and design under system-level requirements.